1. Field of the Invention
This invention relates to system memory configurations and, more particularly, to the interleaving and de-interleaving of memory.
2. Description of the Related Art
As computer system processors have reached higher performance levels, the need for faster memories has become more evident. However, gains in processor performance have far outpaced gains in memory device performance. Accordingly, various techniques have been employed in an attempt to improve the memory system performance.
For example, in many cases, memory access time may be critical to the satisfactory operation of a particular software application. Depending on the system configuration and size, a computer system may have one or more memory controllers that control multiple banks of memory. In some cases, the way the data is stored in memory may cause bottlenecks. For example, if a particular region or bank of memory is accessed heavily, it may create bandwidth issues and increase latencies which contribute to degraded system performance.
One technique that is used to improve memory latencies and distribute bandwidth is known as interleaving. Interleaving refers to mapping consecutive cache line addresses to different banks, or in multi-memory controller systems, to different memory controllers. In some conventional systems, memory may be interleaved using memory controllers that include a hardware mapper that may match on a given address. The mapper may determine which addresses are mapped to which hardware entity (e.g., bank). Thus, the memory controller mapper can be configured to interleave accesses to consecutive cache line addresses. However, in such conventional systems, it becomes problematic to efficiently interleave a non-power of two number of hardware entities.